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Experimental and Theoretical NANOTECHNOLOGY

About the Journal :

Experimental and Theoretical NANOTECHNOLOGY (ETN) is a multidisciplinary peer-reviewed international journal published three issues a year. It includes specialized research papers, short communications, reviews and selected conference papers in special issues on the characterization, synthesis, processing, structure and properties of different principles and applications of NANOTECHNOLOGY; with focus on advantageous achievements and applications for the specialists in engineering, chemistry, physics and materials science.

ETN covers and publishes all aspects of fundamental and applied researches of experimental and theoretical nanoscale technology dealing with materials synthesis, processing, nanofabrication, nanoprobes, spectroscopy, properties, biological systems, nanostructures, nanoelectronics, nano-optics, nano-mechanics, nanodevices, nanobiotechnology, nanomedicine, nanotoxicology within the scope of the journal. ETN aims to acquire the recent and outstanding researches for the benefit of the human being.



ANALYSIS OF RELIABILITY FOR FAULT TOLERANT DESIGN IN NANO CMOS LOGIC CIRCUIT

The emerging nano scaled electronic devices are Carbon Nanotubes (CNT), Silicon nanowires (SINW), nano CMOS switches etc. In Nano CMOS switches, the devices can be interconnected to build the nano scaled CMOS circuit. In this nano CMOS circuit, faults occur at three levels, such as gate level, circuit level and switch level. This paper focusses on the switch level faults of stuck-open or stuck-off and stuck-short or stuck-on that frequently occurs in CMOS switches. To overcome the switch level faults and to increase the reliability, the fault tolerant technique known as the Quadded Transistor (QT) structure is used. An analytical model has been formulated to determine the probability of failure by analyzing the stuck open and stuck short faults. Also, the model has been formulated by implementing QT structure for the single CMOS NAND2 gate. By the use of analytical formulations, the results has been simulated for the occurrence of minimum to maximum number of defective transistors in CMOS logic circuit.

Keywords: : Nano CMOS; Fault; Reliability.

PACS: 85.35-p; 91.55Jk; 88.50gj.